Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Built-in self-test for signal integrity
Proceedings of the 38th annual Design Automation Conference
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
ATS '02 Proceedings of the 11th Asian Test Symposium
Test Pattern Generation for Signal Integrity Faults on Long Interconnects
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Testing SoC interconnects for signal integrity using extended JTAG architecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new high-speed interconnect crosstalk fault model and compression for test space
WSEAS TRANSACTIONS on COMMUNICATIONS
An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip
Microelectronics Journal
A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC
Microelectronics Journal
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Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, we present an abstract model and a new test pattern generation method of signal integrity problems on interconnects. This approach is achieved by considering the effects for testing inputs and parasitic RLC elements of interconnects. We also develop a framework to deal with arbitrary interconnection topology. Experimental results show that the proposed signal integrity fault model is more exact and more powerful for long interconnects than previous approaches.