SOC test architecture optimization for signal integrity faults on core-external interconnects
Proceedings of the 44th annual Design Automation Conference
MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs
Journal of Electronic Testing: Theory and Applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Highly compact interconnect test patterns for crosstalk and static faults
IEEE Transactions on Circuits and Systems II: Express Briefs
Highly compact interconnect test patterns for crosstalk and static faults
IEEE Transactions on Circuits and Systems II: Express Briefs
Fault tolerant network on chip switching with graceful performance degradation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
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In this paper we develop a new fault model for capacitivecrosstalk in inter-core interconnects. We also develop aframework to generate compact tests for interconnects witharbitrary topologies. Experimental results show that theproposed approach can significantly reduce test application timefor large interconnects. We are in the process of extending theframework to interconnects that include tri-state as well as bi-directionalnets.