An analytical method for finding the maximum crosstalk in lossless-coupled transmission lines
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A new gate delay model for simultaneous switching and its applications
Proceedings of the 38th annual Design Automation Conference
Process-Aggravated Noise (PAN): New Validation and Test Problems
Proceedings of the IEEE International Test Conference on Test and Design Validity
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
Test generation in VLSI circuits for crosstalk noise
ITC '98 Proceedings of the 1998 IEEE International Test Conference
2.3 Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Proceedings of the conference on Design, automation and test in Europe - Volume 2
An empirical study of crosstalk in VDSM technologies
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Proceedings of the conference on Design, automation and test in Europe
A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuits
Proceedings of the 19th ACM Great Lakes symposium on VLSI
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Circuit marginality failures in high performance VLSI circuits are projected to increase due to shrinking process geometries and high frequency design techniques. Capacitive cross coupling between interconnects is known to be a prime contributor to such failures. In this paper, we present novel techniques to model and prioritize capacitive cross-talk faults. Experimental results are provided to show effectiveness of the proposed modeling technique on industrial circuits.