PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A realizable driving point model for on-chip interconnect with inductance
Proceedings of the 37th Annual Design Automation Conference
Efficient inductance extraction via windowing
Proceedings of the conference on Design, automation and test in Europe
CMOS gate delay models for general RLC loading
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Return-limited inductances: a practical approach to on-chip inductance extraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Modeling on-chip inductive effects for interconnects of multi-gigahertz microprocessors remains challenging. SPICE simulation of these effects is very slow because of the large number of mutual inductances. Meanwhile, ignoring the non-linear behavior of drivers in a fast linear circuit simulator results in large errors for the inductive effect. In this paper, a fast and accurate time-domain transient analysis approach is presented, which captures the non-linearity of circuit drivers, the effect of non-ideal ground and de-coupling capacitors in a bus structure. The proposed method models the non-linearity of drivers in conjunction with specific bus geometries. Linearized waveforms at each driver output are incorporated into an interconnect reduced-order simulator for fast transient simulation. In addition, non-ideal ground and de-coupling capacitor models enable accurate signal and ground bounce simulations. Results show that this simulation approach is up-to 68x faster than SPICE while maintaining 95% accuracy.