DAC '96 Proceedings of the 33rd annual Design Automation Conference
Near-optimal critical sink routing tree constructions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The Elmore delay as a bound for RC trees with generalized input signals
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ISPD '99 Proceedings of the 1999 international symposium on Physical design
ISPD '99 Proceedings of the 1999 international symposium on Physical design
FAR-DS: full-plane AWE routing with driver sizing
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Self-reforming routing for stochastic search in VLSI interconnection layout
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Integration, the VLSI Journal
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The inaccuracy of Elmore delay [3] for inter conne ct delay estimation is well-documented. However it remains a popular delay measur e to drive p erformance optimization procedur es such as wire-sizing and topolo gy construction. This p aper studies the merits of incorp orating “b etter-than-Elmore” delay measur es into the optimization process. The proposed delay metrics use a table-lo okup method to incorporatebetter load modeling and approximate the effect of signal slew. We demonstrate that the proposed metrics exhibit a much narrower error distribution than Elmore delay, eliminating Elmore's frequent gross delay over-estimation. Finally we show the improvement in solution quality which can b e had by inc orp orating the new metrics into a timing driven topology construction algorithm.