DAC '96 Proceedings of the 33rd annual Design Automation Conference
Buffered Steiner tree construction with wire sizing for interconnect layout optimization
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
Buffer insertion for noise and delay optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Proceedings of the 2002 international symposium on Physical design
S-Tree: a technique for buffered routing tree synthesis
Proceedings of the 39th annual Design Automation Conference
An O(nlogn) time algorithm for optimal buffer insertion
Proceedings of the 40th annual Design Automation Conference
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Simultaneous routing and buffer insertion with restrictions on buffer locations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Repeater scaling and its impact on CAD
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An O(mn) time algorithm for optimal buffer insertion of nets with m sinks
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Fast buffer insertion considering process variations
Proceedings of the 2006 international symposium on Physical design
Data handling limits of on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
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Buffer insertion is a popular technique to reduce the interconnect delay. The classic buffer insertion algorithm of van Ginneken has time complexity O(n^2), where n is the number of buffer positions. Lillis, Cheng and Lin extended van Ginneken's algorithm to allow b buffer types in time O (b^2 n^2). For modern design libraries that contain hundreds of buffers, it is a serious challenge to balance the speed and performance of the buffer insertion algorithm. In this paper, we present a new algorithm that computes the optimal buffer insertion in O (bn^2) time. The reduction is achieved by the observation that the (Q, C) pairs of the candidates that generate the new candidates must form a convex hull. On industrial test cases, the new algorithm is faster than the previous best buffer insertion algorithms by orders of magnitude.