Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Generation of very large circuits to benchmark the partitioning of FPGA
ISPD '99 Proceedings of the 1999 international symposium on Physical design
ISPD '00 Proceedings of the 2000 international symposium on Physical design
ICGT '02 Proceedings of the First International Conference on Graph Transformation
Proceedings of the 3rd ACM international workshop on Data engineering for wireless and mobile access
Detecting tangled logic structures in VLSI netlists
Proceedings of the 47th Design Automation Conference
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Vertex orderings have been successfully applied to problems in netlist clustering and for system partitioning and layout. We present a vertex ordering construction that encompasses most reasonable graph traversals. Two parameters-an attraction function and a window-provide the means for achieving various graph traversals and addressing particular clustering requirements. We then use dynamic programming to optimality split the vertex ordering into a multiway clustering. Our approach outperforms several clustering methods in the literature in terms of three distinct clustering objectives. The ordering construction, by itself, also outperforms existing graph ordering constructions for this application. Tuning our approach to "meta-objectives", particularly clustering for two-phase Fiduccia-Mattheyses bipartitioning, remains an open area of research.