High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Utilization of multiport memories in data path synthesis
DAC '93 Proceedings of the 30th international Design Automation Conference
Discrete Optimization Algorithms with Pascal Programs
Discrete Optimization Algorithms with Pascal Programs
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
ISPD '00 Proceedings of the 2000 international symposium on Physical design
System-level interconnect architecture exploration for custom memory organizations
Proceedings of the 14th international symposium on Systems synthesis
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Mapping Computation with No Memory
UC '09 Proceedings of the 8th International Conference on Unconventional Computation
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With the increasing use of register files as storage elements in integrated circuits, the problem of assigning data variables to ports of register files has assumed significance. The assignment involves simultaneous optimization of several cost functions, namely, number of register files, number of registers and access ports per register file, and the interconnect both internal and external to memories. In this paper, we refer to multiplexers, busses, and tristate switches when we refer to interconnect. The objective of this paper is to describe graph-theoretic optimization algorithms for the assignment problem. The allocation system described in this paper (SOUPS) accepts a scheduled data flow graph as input and performs (i) assignment of variables to a minimal number of registers, (ii) assignments of registers to a minimal number of register files, (iii) assignment of registers to ports of the register files using minimal interconnect within the register files, and (iv) assignment of ports of the register files to terminals of functional modules using minimal interconnect outside the register files. We describe experimental results on several benchmark problems from literature with substantial improvements.