ISPD '00 Proceedings of the 2000 international symposium on Physical design
Sequential Permissible Functions and their Application to Circuit Optimization
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Symbolic support graph: a space efficient data structure for incremental tabled evaluation
ICLP'05 Proceedings of the 21st international conference on Logic Programming
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Computing the set of reachable states of a finite state machine, is an important component of many problems in the synthesis and formal verification of digital systems. The process of design is usually iterative, and the designer may modify and recompute information many times, and reachability is called each time the designer modifies the system because current methods for reachability analysis are not incremental. Unfortunately, the representation of the reachable states that is currently used in synthesis and verification, is inherently non updatable (O. Coudert and J.C. Madre, 1990). We solve this problem by presenting alternate ways to represent the reachable set, and incremental algorithms that can update the new representation each time the designer changes the system. The incremental algorithms use the reachable set computed at a previous iteration, and information about the changes to the system to update it, rather than compute the reachable set from the beginning. This results in computational savings, as demonstrated by the results.