Theoretical limits for signal reflections due to inductance for on-chip interconnections

Authors:
D. Deschacht;G. Servel;F. Huret;E. Paleczny;P. Kennis
Affiliations:
Laboratoire d'Informatique, de Robotique et de Microélectronique, U.M.R. C.N.R.S. 5506, 161, rue ADA, 34392 Montpellier Cedex 5, France;Laboratoire d'Informatique, de Robotique et de Microélectronique, U.M.R. C.N.R.S. 5506, 161, rue ADA, 34392 Montpellier Cedex 5, France;Institut d'Electronique et de Microélectronique du Nord, U.M.R. C.N.R.S. 9929, Département Hyperfréquences et Semiconducteurs, Cité Scientifique, Avenue Poincaré, B.P. 69, ...;Institut d'Electronique et de Microélectronique du Nord, U.M.R. C.N.R.S. 9929, Département Hyperfréquences et Semiconducteurs, Cité Scientifique, Avenue Poincaré, B.P. 69, ...;Institut d'Electronique et de Microélectronique du Nord, U.M.R. C.N.R.S. 9929, Département Hyperfréquences et Semiconducteurs, Cité Scientifique, Avenue Poincaré, B.P. 69, ...
Venue:
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Year:
2000

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