Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
Figures of merit to characterize the importance of on-chip inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Equivalent Elmore delay for RLC trees
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
Exploiting the on-chip inductance in high-speed clock distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
A new RLC buffer insertion algorithm
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
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The effects of inductance on repeater insertion in RLC trees is the focus of this paper. An algorithm is introduced to insert and size repeaters within an RLC tree to optimize a variety of possible cost functions such as minimizing the maximum path delay, the skew between branches, or a combination of area, power, and delay. The algorithm has a complexity proportional to the square of the number of possible repeater positions, permitting a repeater solution to be chosen that is close to the global minimum. The repeater insertion algorithm is used to insert repeaters within several copper-based interconnect trees to minimize the maximum path delay based on both an RC model and an RLC model. The two buffering solutions are compared using the AS/X dynamic circuit simulator. It is shown that as inductance effects increase, the area and power consumed by the inserted repeaters to minimize the path delays of an RLC tree decreases. By including inductance in the repeater insertion methodology, the interconnect is modeled more accurately as compared to an RC model, permitting average savings in area, power, and delay of 40.8%, 15.6%, and 6.7%, respectively, for a variety of copper-based interconnect trees from a 0.25 &mgr;m CMOS technology. The average savings in area, power, and delay increases to 62.2%, 57.2%, and 9.4%, respectively, when using five times faster devices with the same interconnect trees.