A 3.4Gbps transmitter for multi-serial data communication using pre-emphasis method

Authors:
Kangjik Kim;Kisang Jung;Chimin Park;Wonki Park;Sungchul Lee;Seongik Cho
Affiliations:
The Department of Electronics Engineering, Chonbuk National University, Jeonju, Jeonbuk, South Korea;The Department of Electronics Engineering, Chonbuk National University, Jeonju, Jeonbuk, South Korea;The Department of Electronics Engineering, Chonbuk National University, Jeonju, Jeonbuk, South Korea;Korea Electronics Technology Institute;Korea Electronics Technology Institute;The Department of Electronics Engineering, Chonbuk National University, Jeonju, Jeonbuk, South Korea
Venue:
CISST'10 Proceedings of the 4th WSEAS international conference on Circuits, systems, signal and telecommunications
Year:
2010

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Abstract

This paper is intended as design of a 3.4Gb/s transmitter (TX) for multi-channel communication. It can be applied high-speed serial link system such as DVI, HDMI etc. This TX circuit can be classified into three main blocks and one additional block: a PLL (Phase Locked Loop) block for a clock distribution, a MUX (multiplexer) block as a data serializer and an output buffer stage for a driving of output data stream. The additional block is a PRBS circuit for a separated PHY verification. The output buffer consists of three parts (pre-driver, CML main driver and pre-emphasis driver). Especially, the pre-emphasis method is applied to improve the effect of ISI. The fabricated TX was designed using 0.18µm 1P5M CMOS technology and was verified on 3.4Gbps output data rate by measurement results. An eye-opening is shown about 0.8UI/700mV on output data. The fabricated chip has been designed and laid using 0.18µm 1P5M CMOS technology.