Asynchronous Circuits for Low Power: A DCC Error Corrector
IEEE Design & Test
CMOS current steering logic for low-voltage mixed-signal integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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DATE '00 Proceedings of the conference on Design, automation and test in Europe
Low Switching Noise CMOS Circuit Design Strategy Based on Regular Self-Timed Structures
MWSCAS '98 Proceedings of the 1998 Midwest Symposium on Systems and Circuits
A DFT Technique for Analog-to-Digital Converters with digital correction
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
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PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
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This paper presents an application where a self-timed approach reduces the switching noise in a mixed analog-digital circuit. Switching noise is of important concern in mixed signal systems, since it limits the performances of the analog part. Specifically, the digital core of an Analog to Digital converter has been designed following both a synchronous design style and another self-timed. Comparison between both versions shows the self-timed implementation reduce up to 50% the switching noise corresponding to the synchronous implementation.