Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
A case study on the implementation of the Illinois Scan Architecture
Proceedings of the IEEE International Test Conference 2001
Tailoring ATPG for embedded testing
Proceedings of the IEEE International Test Conference 2001
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Two-dimensional test data compression for scan-based deterministic BIST
Proceedings of the IEEE International Test Conference 2001
Test vector encoding using partial LFSR reseeding
Proceedings of the IEEE International Test Conference 2001
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Scan Vector Compression/Decompression Using Statistical Coding
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Test Data Compression for System-on-a-Chip Using Golomb Codes
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Virtual Scan Chains: A Means for Reducing Scan Length in Cores
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Efficient Seed Utilization for Reseeding based Compression
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A MIXED MODE BIST SCHEME BASED ON RESEEDING OF FOLDING COUNTERS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
REDUCING TEST DATA VOLUME USING EXTERNAL/LBIST HYBRID TEST PATTERNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Packet-Based Input Test Data Compression Techniques
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
Reducing Test Application Time Through Test Data Mutation Encoding
Proceedings of the conference on Design, automation and test in Europe
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
On Test Data Volume Reduction for Multiple Scan Chain Designs
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Frugal linear network-based test decompression for drastic test cost reductions
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Survey of Test Vector Compression Techniques
IEEE Design & Test
State skip LFSRs: bridging the gap between test data compression and test set embedding for IP cores
Proceedings of the conference on Design, automation and test in Europe
Multilevel-Huffman test-data compression for IP cores with multiple scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improving linear test data compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Deviation-based LFSR reseeding for test-data compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Computers and Electrical Engineering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Time-multiplexed compressed test of SOC designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Correlation-based rectangular encoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Capture-power-aware test data compression using selective encoding
Integration, the VLSI Journal
Test data compression using selective encoding of scan slices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
A new scheme for combinational linear expansion isproposed for decompression of scan vectors. It has thecapability to adjust the width of the linear expansion each clockcycle. This eliminates the requirement that every scan bit-slicebe in the output space of the linear decompressor. Depending onhow specified the current bit-slice is, the decompressor may loadall scan chains or may load only a subset of the scan chains.This provides the nice feature that any scan vector can begenerated using the proposed scheme regardless of the numberor distribution of the specified bits. Thus, the proposed schemeallows the use of any ATPG procedure without any constraints.Moreover, it allows greater compression to be achieved thanfixed width expansion techniques since the ratio of the number ofscan chains to the number of tester channels can be scaled muchlarger. A procedure for designing and optimizing the adjustablewidth decompression hardware and obtaining the compresseddata is described. Experimental data indicates that the proposedscheme is simple yet very effective.