Condensed Linear Feedback Shift Register (LFSR) Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers - The MIT Press scientific computation series
Partitioning circuits for inproved testability
Proceedings of the fourth MIT conference on Advanced research in VLSI
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
An efficient partitioning strategy for pseudo-exhaustive testing
DAC '93 Proceedings of the 30th international Design Automation Conference
Novel Test Pattern Generators for Pseudo-Exhaustive Testing
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
PEST: a tool for implementing pseudo-exhaustive self test
EURO-DAC '90 Proceedings of the conference on European design automation
Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing
IEEE Transactions on Computers
Verification Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers
Logic Test Pattern Generation Using Linear Codes
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
The Weighted Syndrome Sums Approach to VLSI Testing
IEEE Transactions on Computers
Exhaustive Test Pattern Generation with Constant Weight Vectors
IEEE Transactions on Computers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reducing scan shifts using configurations of compatible and folding scan trees
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
This paper presents a new test architecture, calledTree-LFSR/SR, to more effectively generate pseudo-exhaustive test patterns for combinational VLSI circuits.Instead of using a single scan chain, the proposed testarchitecture routes a scan tree driven by the LFSR togenerate all possible input patterns for each output cone.The new test architecture is able to take advantages ofboth signal sharing and signal reuse. The benefits are:(1) the hardware overhead can be greatly reduced by saving routing area and XOR circuits, and (2) the difficultyof test architecture synthesis can be eased by accelerating the searching process of appropriate residues. TheTree-LFSR/SR configuration is then extended, if necessary, by adding XOR networks to deal with more complex input-output relations. An efficient method to directly synthesize the XOR network is also included. Experimental results obtained by simulating combinationalbenchmark circuits are very encouraging.