The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Reorganizing Circuits to Aid Testability
IEEE Design & Test
Optimal Configuring of Multiple Scan Chains
IEEE Transactions on Computers
Optimal Sequencing of Scan Registers
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Control strategies for chip-based DFT/BIST hardware
ITC'94 Proceedings of the 1994 international conference on Test
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