SIESTA: a multi-facet scan design system
EURO-DAC '92 Proceedings of the conference on European design automation
| Hi-index | 0.00 |
A method of partitioning a circuit canonically into disjoint subcircuits and to group similarly connected storage elements is described. The method is being used in a program called Crete (for Clouding, hierarchical Reorganization, Equivalence determination, Test-methodology embedding, and Editing). Crete partitions and reorganizes the hierarchical description of a circuit so that the designer can apply design-for-testability or built-in self-test techniques to the new hierarchy. The partitioning preserves the designer's circuit hierarchy as much as possible to allow the easy identification of equivalence among partitioned groups. The method reduces the time needed for both test generation and test application in designs that use full scan, partial scan, and built-in self-test techniques. Results for a Viterbi decoder validate the concepts underlying Crete.