Test Schedules for VLSI Circuits Having Built-In Test Hardware
IEEE Transactions on Computers - The MIT Press scientific computation series
A unified approach to input-output encoding for FSM state assignment
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
SIESTA: a multi-facet scan design system
EURO-DAC '92 Proceedings of the conference on European design automation
Minimal area merger of finite state machine controllers
EURO-DAC '92 Proceedings of the conference on European design automation
Merging multiple FSM controllers for DFT/BIST hardware
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Designing and Implementing an Architecture with Boundary Scan
IEEE Design & Test
HIST: A Methodology for the Automatic Insertion of a Hierarchical Self Test
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
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We present strategies for controlling on-chip design-for-test (DFT) and built-in self-test (BIST) circuitry under a partially distributed test control architecture. These include mechanisms for broadcasting control information from an integrated TAP controller over an internal test bus, techniques for creating symbolic descriptions of local decoders that employ this information to control test resources, and algorithms for encoding the bus information. The encoding algorithms minimize a two-level implementation of the integrated TAP controller and/or the distributed decoders. These control strategies are IEEE 1149.1 boundary scan standard compliant and are applicable to both simple and complex DFT/BIST methodologies including those that employ multifunction and/or reconfigurable test registers and reconfigurable scan chains.