Digital logic testing and simulation
Digital logic testing and simulation
Configuration of a boundary scan chain for optimal testing of clusters of non boundary scan devices
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
An IEEE 1149.1 Compliant Test Control Architecture
Journal of Electronic Testing: Theory and Applications
OMA DM-based remote software fault management for mobile devices
International Journal of Network Management
Paper: Reconfigurable VLSI/WSI multipipelines
Parallel Computing
Control strategies for chip-based DFT/BIST hardware
ITC'94 Proceedings of the 1994 international conference on Test
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A description is given of a standardized structured test methodology based on the boundary-scan proposal from the Joint Test Action Group (JTAG), which is now IEEE proposed standard P1149.1. Boundary scan does not address testability at the IC level, primarily because there is no standard for designing built-in self-testing (BIST) circuits. An architecture called the hierarchical testable, or H-testable, architecture that is compatible with the JTAG boundary-scan standard for PCB testing and provides BIST at the IC level is presented. The two have been merged, ensuring testability of the hardware from the printed-circuit-board level down to integrated-circuit level. In addition, the architecture has built-in self-test at the IC level. The authors have implemented this design using a self-test compiler.