Test Scheduling and Control for VLSI Built-in Self-Test
IEEE Transactions on Computers
The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
BIDES: a BIST design expert system
Journal of Electronic Testing: Theory and Applications
Minimal area merger of finite state machine controllers
EURO-DAC '92 Proceedings of the conference on European design automation
HIST: a hierarchical self test methodology for chips, boards, and systems
Journal of Electronic Testing: Theory and Applications
Merging multiple FSM controllers for DFT/BIST hardware
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Arithmetic built-in self-test for embedded systems
Arithmetic built-in self-test for embedded systems
Designing and Implementing an Architecture with Boundary Scan
IEEE Design & Test
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Optimal Configuring of Multiple Scan Chains
IEEE Transactions on Computers
Control Strategies for Chip-Based DFT/BIST Hardware
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Testability, Debuggability, and Manufacturability Features of the UltraSPARCTM-I Microprocessor
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Pentium® Pro Processor Design for Test and Debug
Proceedings of the IEEE International Test Conference
Test Features of the HP PA7100LC Processor
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Asynchronous multiple scan chains
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
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A general method for determining whether a certain design is initializable, and for generating its initialization sequence, is presented in this paper. This method is based on structural decomposition of the circuit, and can handle both logical ...