Introducing Core-Based System Design
IEEE Design & Test
Optimal Configuring of Multiple Scan Chains
IEEE Transactions on Computers
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On Using IEEE P1500 SECT for Test Plug-n-Play
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Control-ready architecture for self-testing in programmable logical matrix structures
Automation and Remote Control
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Editor's note:The tradeoff between IP protection and SoC-level test optimization has been an issue for some time. The more IP providers protect their IP, the less flexibility system developers have to control test costs and fault coverage. Here, a new approach dynamically extracts IP-related test information for optimizing SoC testing without jeopardizing IP protection.ýYervant Zorian, Virage Logic