Digital logic testing and simulation
Digital logic testing and simulation
The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
An analytical approach to the partial scan problem
Journal of Electronic Testing: Theory and Applications
A test methodology for finite state machines using partial scan design
Journal of Electronic Testing: Theory and Applications
A New Class of Sequential Circuits with Combinational Test Generation Complexity
IEEE Transactions on Computers
Structured Logic Testing
ATS '00 Proceedings of the 9th Asian Test Symposium
Sequential Circuits with combinational Test Generation Complexity
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Combinational Test Generation for Acyclic Sequential Circuits using a Balanced ATPG Model
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
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It is known that a class of acyclic sequential circuitscalled balanced circuits can be tested by combinationalATPG. The first contribution of this paper is a modified andefficient combinational single fault ATPG method for anygeneral (not necessarily balanced) acyclic circuit. Withoutinserting real hardware, we create a "balanced" ATPGmodel of the circuit in which all reconverging paths have thesame sequential depth. Some primary inputs are duplicatedand each combinational ATPG vector for this model circuitis transformed into a test sequence. Although no time-frameexpansion is used, a small set of faults still map onto multiplefaults. Those are identified and dealt with again by thesingle fault combinational ATPG. The results show nearlyan order of magnitude or greater saving in the ATPG CPUtime over sequential ATPG. The second contribution consistsof new partial-scan algorithms to obtain three subclassesof acyclic circuits, namely, internally balanced, balanced,and strongly balanced, which have been described in theliterature. Results on ISCAS '89 circuits show that suchstructures require extra scan overhead, sometimes almostapproaching that of full-scan, and their advantages in ATPGare marginal considering the present contribution.