COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Compact two-pattern test set generation for combinational and full scan circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On Generating High Quality Tests for Transition Faults
ATS '02 Proceedings of the 11th Asian Test Symposium
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Proceedings of the conference on Design, automation and test in Europe - Volume 2
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
IEEE Transactions on Computers
The ATPG Conflict-Driven Scheme for High Transition Fault Coverage and Low Test Cost
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
On-chip Generation of the Second Primary Input Vectors of Broadside Tests
DFT '09 Proceedings of the 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
On test generation with test vector improvement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multipattern Scan-Based Test Sets With Small Numbers of Primary Input Sequences
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Tester limitations may impose certain constraints on the primary input vectors applicable as part of a two-pattern test for delay faults. Under these constraints, the primary input vectors may be held constant, or the second primary input vector of a test may be obtained by a single shift of a scan chain relative to the first. The goal of this brief is to study the differences in achievable transition fault coverage between various primary input constraints that are similar to the commonly used ones of holding or shifting primary input vectors. This brief also studies the possibility of combining the constraints in order to increase the transition fault coverage. The combination requires a fixed and circuit-independent hardware structure similar to the case where shifting of primary input vectors is used. This study is done using test sets that consist of both broadside and skewed-load tests in order to maximize the transition fault coverage.