Multiple-output propagation transition fault test
Proceedings of the IEEE International Test Conference 2001
Delay Defect Screening using Process Monitor Structures
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Timing-based delay test for screening small delay defects
Proceedings of the 43rd annual Design Automation Conference
Selecting High-Quality Delay Tests for Manufacturing Test and Debug
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
Towards acceleration of fault simulation using graphics processing units
Proceedings of the 45th annual Design Automation Conference
Efficient fault simulation on many-core processors
Proceedings of the 47th Design Automation Conference
FSimGP^2: An Efficient Fault Simulator with GPGPU
ATS '10 Proceedings of the 2010 19th IEEE Asian Test Symposium
A parallel branch and bound algorithm for test generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test pattern generation using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This is a massively parallel ATPG that explores device-level, block-level and word-level parallelism in GPU. Eight-detect transition fault ATPG experiments on large benchmark circuits show that our technique achieved 5.6 and 1.6 times speedup compared with a single-core and 8-core CPU commercial tool, respectively. Test patterns selected from our test set are about the same length and quality as those selected from commercial N-detect ATPG. To the best of our knowledge, this is the first proposed GPU-based ATPG algorithm.