Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Certified timing verification and the transition delay of a logic circuit
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Generation of Compact Delay Tests by Multiple-Path Activation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences
Journal of Electronic Testing: Theory and Applications
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences
ETW '00 Proceedings of the IEEE European Test Workshop
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Diagnosis framework for locating failed segments of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Published research on delay fault testing has largely focused on generating test vector pairs (called delay fault tests) to detect delay faults in a circuit. Little attention has been paid to the diagnosability of delay faults-in the quest for generating tests which can simultaneously detect a delay fault on many paths, one loses the ability to determine which paths caused a chip failure. Since fabrication process perturbations contribute to the occurrence of delay faults, one would also like to determine the likely fabrication process parameter values given that a chip has failed for a set of delay fault tests. We present a framework to detect which parts of the circuit are likely to have caused a chip failure for a set of delay fault tests, and to find the associated fabrication process parameter deviations from their nominal values. This diagnosis is done by using a path sensitization mechanism to find the path delay conditions for which the chip exhibits a delay fault for a subset of the applied tests, followed by a statistical analysis to locate the likely fabrication process parameter value combinations and the parts of the circuit which are likely to have caused the failure. We present results of experiments performed an some ISCAS'89 benchmark circuits, and also relate the slack of a path segment to its probability of contributing to the circuit failure.