Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
The Transduction Method-Design of Logic Networks Based on Permissible Functions
IEEE Transactions on Computers
NEST: A non-enumerative test generation method for path delay faults in combinational circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Delay fault coverage and performance tradeoffs
DAC '93 Proceedings of the 30th international Design Automation Conference
Multi-level logic optimization by implication analysis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Random pattern testable logic synthesis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Design-for-testability for path delay faults in large combinatorial circuits using test-points
DAC '94 Proceedings of the 31st annual Design Automation Conference
Fast identification of robust dependent path delay faults
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits
IEEE Transactions on Computers
Sequential logic optimization by redundancy addition and removal
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
An efficient non-enumerative method to estimate path delay fault coverage
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
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We propose a resynthesis mthod that modifies a given circuit to reduce the number of paths in the circuit and thus improve its path delay fault testability. The resynthesis procedure is bawd on replacing subcircuits of the given circuit by structures called comparison units. A subcircuit can be replaced by a comparsion unit if it implements a function belonging to the class of comparison functions defined here. Comparison units are fully testable for stuck-at faults and for path delay faults. In addition, they have small numbers of paths and gates. These properties make them effective building blocks for resynthesis to improve the path delay fault testability of a ciruit. Experimental results demonstrate considerablereductions in the number of paths and increased path delay fault testability. These are achieved without increasing the number of gates, or the number of gates along the longest path in the circuit. The random pattern testability for stuck-at faults remains unchanged.