IEEE Design & Test
Deep Submicron: Is Test Up to the Challenge?
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Design for Test Approaches to Mixed-Signal Testing
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A design-for-test structure for optimising analogue and mixed signal IC test
EDTC '95 Proceedings of the 1995 European conference on Design and Test
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A high frequency analog IC testing technique using a periodic input stimuli and a sequential undersampling algorithm has been developed. This algorithm overcomes many of the loading problems associated with high speed analog signal testing. The utility of the undersampling technique was shown in previous work using a 1.2 μm CMOS prototype IC. This paper expands that work by improving the performance of the original sampling circuits, investigating the possibility of generating control signals on-chip to reduce test cost, and developing a structured analog Design For Testability (DFT) approach. This approach can be used for high speed testing and is based upon undersampling techniques used in sampling oscilloscopes and mixed-signal testers.