Improving the testability of switched-capacitor filters
Analog Integrated Circuits and Signal Processing - Joint special issue on analog and mixed-signal testing.
Catastrophic Defects Oriented Testability Analysis of a Class AB Amplifier
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Analogue Fault Simulation Based on Layout-Dependent Fault Models
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Very-Low-Voltage Testing for Weak CMOS Logic ICs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Design for Testability of a Modular, Mixed Signal Family of VLSI Devices
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
ABILBO: Analog BuILt-in Block Observer
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Design for Test of Crystal Oscillators: A Case Study
Journal of Electronic Testing: Theory and Applications
A digital partial built-in self-test structure for a high performance automatic gain control circuit
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Mixed Signal DFT at GHz Frequencies
Journal of Electronic Testing: Theory and Applications
A design-for-test technique for multistage analog circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
Defect-Oriented Experiments in Fault Modelling and Fault Simulation of Microsystem Components
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A new quality estimation methodology for mixed-signal and analogue ICs
EDTC '97 Proceedings of the 1997 European conference on Design and Test
11.3 Mixed Signal DFT at GHz Frequencies
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
17.2 A Design for Testability Study on a High Performance Automatic Gain Control Circuit
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
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A new Design-for-Test (DfT) structure based on a configurable operational amplifier, referred to as a "swap amp" is presented that allows access to embedded analogue blocks. The structure has minimal impact on circuit performance and has been evaluated on a custom designed Phase Locked Loop (PLL) structure. A test chip containing faulty and fault free versions of this PLL structure, with and without DfT modifications, has been fabricated and an evaluation of this DfT scheme based on the swap-amp structure carried out. It is shown that for embedded analogue blocks, the DfT strategy can not only improve and simplify analogue and mixed signal IC test, but can also be used for diagnostics.