Incorporating Multi-Chip Module Packaging Constraints into System Design

  • Authors:

  • Vivek Garg;Steve Lacy;David E. Schimmel;Darrell Stogner;Craig Ulmer;D. Scott Wills;Sudhakar Yalamanchili

  • Affiliations:

  • Packaging Research Center, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia;Packaging Research Center, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia;Packaging Research Center, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia;Packaging Research Center, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia;Packaging Research Center, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia;Packaging Research Center, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia;Packaging Research Center, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia

  • Venue:
  • EDTC '96 Proceedings of the 1996 European conference on Design and Test
  • Year:
  • 1996

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Abstract

Computer system design addresses the optimization of metrics such as cost, performance, power, and reliability in the presence of physical constraints. The advent of large area, low cost Multi-Chip Modules (MCM) will lead to a new class of optimal system designs. This paper explores the early analysis of the impact of packaging technology on this design process. Our goal is to develop a suite of tools to evaluate computing system architectures under the constraints of various technologies. The design of the memory hierarchy in high speed microprocessors is used to explore the nature and type of trade-offs that can be made during the conceptual design of computing systems.