Analog VLSI and neural systems
Analog VLSI and neural systems
Circuit implementation of a 300-MHz 64-bit second-generation CMOS Alpha CPU
Digital Technical Journal - Special 10th anniversary issue
Clocking optimization and distribution in digital systems with scheduled skews
Clocking optimization and distribution in digital systems with scheduled skews
Design of a 10GHz clock distribution network using coupled standing-wave oscillators
Proceedings of the 40th annual Design Automation Conference
Analysis and verification of interconnected rings as clock distribution networks
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A multi-level transmission line network approach for multi-giga hertz clock distribution
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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This paper presents a new form of integrated ring oscillator, the Cooperative Ring Oscillator (CRO), in which the controllable delay elements are distributed throughout a VLSI chip. Specifically, each stage of the CRO consists of many electrically parallel delay elements that are spatially distributed. The high degree of parallelism in the CRO provides strong signal aggregation that significantly reduces the skew within each clock phase. The CRO performs both clock generation and clock delivery, thus unifying the tasks of the oscillator, clock buffers, and distribution network into a single circuit. The strength of the CRO technique is that it can deliver multiple, low-skew clock phases to all areas of a large VLSI device at a cost in chip resources comparable to that of current single-phase clock distribution techniques. This strength creates the opportunity for system designers to make extensive use of muli-phase logic techniques to improve system performance.