Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
IC power distribution challenges
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Simultaneous switching noise in on-chip CMOS power distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power grid physics and implications for CAD
Proceedings of the 43rd annual Design Automation Conference
Spectral analysis of the on-chip waveforms to generate guidelines for EMC-aware design
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Clock distribution techniques for Low-EMI design
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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In modern digital ICs, the increasing demand for performance and throughput requires operating frequencies of hundreds of megahertz, and in several cases exceeding the gigahertz range. Following the technology scaling trends, this request will continue to rise, thus increasing the electromagnetic interference (EMI) generated by electronic systems. The enforcement of strict governmental regulations and international standards, mainly (but not only) in the automotive domain, are driving new efforts towards design solutions for electromagnetic compatibility (EMC). Hence, EMC/EMI is rapidly becoming a major concern for high-speed circuit and package designers. The on-chip power rail noise is one of the most detrimental sources of electromagnetic (EM) conducted emissions, since it propagates to the board through the power and ground I/O pads. In this work we investigate the impact of power rail noise on EMI, and we show that by limiting this noise source it is possible to drastically reduce the conducted emissions. Furthermore, we present a transistor-level lumped-element simulation model of the system power distribution network (PDN) that allows chip, package, and board designers to asses the power integrity and predict the conducted emissions at critical chip I/O pads. The experimental results obtained on an industrial microcontroller for automotive applications demonstrate the effectiveness of our approach.