Low-power operation using self-timed circuits and adaptive scaling of the supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Handbook of Applied Cryptography
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Examining Smart-Card Security under the Threat of Power Analysis Attacks
IEEE Transactions on Computers
Improving Smart Card Security Using Self-Timed Circuits
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
An Investigation into the Security of Self-Timed Circuits
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Design and Analysis of Dual-Rail Circuits for Security Applications
IEEE Transactions on Computers
Design Method for Constant Power Consumption of Differential Logic Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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CRYPTO'11 Proceedings of the 31st annual conference on Advances in cryptology
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Microelectronics Journal
Information theoretic and security analysis of a 65-nanometer DDSLL AES S-box
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
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This paper describes two new dynamic differential self-timed logic families that can be used either to implement low-power security components or low-power high-speed self-timed circuits. Electrical simulations in 0.13@mm partially depleted (PD) SOI CMOS under a V"d"d of 1.2V have shown that the substitution box (S-box), a module of the Khazad cipher algorithm, implemented with the improved feedback low swing current mode logic (IFLSCML) features a power consumption standard deviation almost five times smaller than that of the self-timed DDCVSL one, while consuming 37% less. On the other hand, the 8b CLA implemented with dynamic differential swing limited logic (DDSLL) features a power delay product about 19% lower than that of its counterpart implemented with self-timed DDCVSL.