Multiplicative Masking and Power Analysis of AES
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Improving Smart Card Security Using Self-Timed Circuits
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Power-Analysis Attack on an ASIC AES implementation
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
Design and Analysis of Dual-Rail Circuits for Security Applications
IEEE Transactions on Computers
Provably secure masking of AES
SAC'04 Proceedings of the 11th international conference on Selected Areas in Cryptography
A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Hi-index | 0.00 |
In recent years several successful GALS realizations have been presented. The core of a GALS system is a locally synchronous island that is designed using industry standard synchronous design methodologies. In principle, any functional synchronous block can be encapsulated as a locally synchronous island to form a GALS module. There are, however, several important trade-offs and design decisions involved in doing so. Partitioning a design into several GALS compatible modules is still the most difficult task facing GALS system designers. The controlling state machine of a synchronous functional block may need to be enhanced significantly to accommodate varying latencies involved in data transfers between GALS modules. Such design challenges can not be easily generalized, and in this paper, are presented based on the experiences of designing a GALS system that implements a cryptographic algorithm. The example design uses the GALS methodology to improve resistance against cryptographic power attacks. The problem of side channel attacks against hardware implementations of cryptographic algorithms are briefly presented first, and the GALS architecture featuring several countermeasures against such attacks is introduced. The main part of the paper concentrates on the design decisions involved in the development of this architecture.