Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
A brief history of the data encryption standard
Internet besieged
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
CRYPTO '96 Proceedings of the 16th Annual International Cryptology Conference on Advances in Cryptology
Differential Power Analysis in the Presence of Hardware Countermeasures
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A novel AES cryptographic core highly resistant to differential power analysis attacks
Proceedings of the 21st annual symposium on Integrated circuits and system design
A Novel Countermeasure Enhancing Side Channel Immunity in FPGAs
ENICS '08 Proceedings of the 2008 International Conference on Advances in Electronics and Micro-electronics
Two-phase synchronization with sub-cycle latency
Integration, the VLSI Journal
Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC
Electronic Notes in Theoretical Computer Science (ENTCS)
Ways to enhance differential power analysis
ICISC'02 Proceedings of the 5th international conference on Information security and cryptology
Evaluation on FPGA of triple rail logic robustness against DPA and DEMA
Proceedings of the Conference on Design, Automation and Test in Europe
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Side channels attacks (SCA) are very effective and low cost methods to extract secret information from supposedly secure cryptosystems. Differential Power Analysis (DPA) and Differential Electromagnetic Analysis (DEMA) are among the most cited attack types. The traditional synchronous design flow used to create such systems favors the leakage of information that enables attackers to draw correlations between data processes and circuit power consumption or electromagnetic radiations. By using well known analysis techniques these correlations may allow that an attacker retrieve secret cryptographic keys. In recent years, several countermeasures against SCA have been proposed. Globally Asynchronous Locally Synchronous (GALS) and fully asynchronous design methods appear as alternatives to design tamper resistant cryptosystems. However, according to previous works they use to achieve this with significant area, throughput, latency and power penalties. This paper proposes a new GALS pipeline architecture for the Data Encryption Standard (DES) that explores the trade-off between circuit area and robustness. Robustness is enhanced by replicating the DES hardware structure in asynchronously communicating module instances, coupled with self-varying operating frequencies. Designs prototyped on FPGAs using the proposed technique and submitted to DEMA attacks presented promising robustness against attacks and throughput superior to previously reported results.