A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
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Side channel attacks (SCAs) are very effective in extracting information from algorithmically secure systems. Since, the earliest reports of attacks exploiting side channels such as power consumption, timing behavior and electromagnetic radiation etc., the countermeasures to resist such attacks have also been proposed. FPGAs originally thought to be resistant to such attacks because of some inherent characteristics were also found to leak information over the side channels. Overtime, SCA countermeasures have been proposed that continue to fade away as resistant attack techniques are developed. In this article an FPGA implementation of a multi–clock system with cipher embodiment, incorporating a novel countermeasure to resist SCAs, is presented. The proposed methodology of embedding single inverter ring oscillators (SIROs) within the synchronous cores helps improve immunity against electromagnetic, fault and glitch attacks, while the introduction of frequency hopping by randomly varying frequency driving the cipher hardens the system against power and timing attacks. The incorporated countermeasure enhances the immunity of FPGA based implementation against multiple types of SCAs without adversely affecting cost or performance.