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Delay Insensitive Encoding and Power Analysis: A Balancing Act
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DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Power balanced gates insensitive to routing capacitance mismatch
Proceedings of the conference on Design, automation and test in Europe
Dual-rail random switching logic: a countermeasure to reduce side channel leakage
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
A digital design flow for secure integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Exploiting dual-output programmable blocks to balance secure dual-rail logics
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
A secure D Flip-Flop against side channel attacks
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
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Side channel attacks are known to be efficient techniques to retrieve secret data. In this context, this paper concerns the evaluation of the robustness of triple rail logic against power and electromagnetic analyses on FPGA devices. More precisely, it aims at demonstrating that the basic concepts behind triple rail logic are valid and may provide interesting design guidelines to get DPA resistant circuits which are also more robust against DEMA.