CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
DES and Differential Power Analysis (The "Duplication" Method)
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Secure FPGA circuits using controlled placement and routing
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Evaluating the robustness of secure triple track logic through prototyping
Proceedings of the 21st annual symposium on Integrated circuits and system design
Evaluation of the Masked Logic Style MDPL on a Prototype Chip
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Masking and Dual-Rail Logic Don't Add Up
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Divided Backend Duplication Methodology for Balanced Dual Rail Routing
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
A Practical DPA Countermeasure with BDD Architecture
CARDIS '08 Proceedings of the 8th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks
IEEE Transactions on Computers
Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs
SSIRI '08 Proceedings of the 2008 Second International Conference on Secure System Integration and Reliability Improvement
Isolated WDDL: A Hiding Countermeasure for Differential Power Analysis on FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks
EUROCRYPT '09 Proceedings of the 28th Annual International Conference on Advances in Cryptology: the Theory and Applications of Cryptographic Techniques
Place-and-route impact on the security of DPL designs in FPGAs
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
Theoretical and Practical Aspects of Mutual Information Based Side Channel Analysis
ACNS '09 Proceedings of the 7th International Conference on Applied Cryptography and Network Security
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow
RECONFIG '09 Proceedings of the 2009 International Conference on Reconfigurable Computing and FPGAs
BCDL: a high speed balanced DPL for FPGA with global precharge and no early evaluation
Proceedings of the Conference on Design, Automation and Test in Europe
Evaluation on FPGA of triple rail logic robustness against DPA and DEMA
Proceedings of the Conference on Design, Automation and Test in Europe
Provably secure masking of AES
SAC'04 Proceedings of the 11th international conference on Selected Areas in Cryptography
Dual-rail random switching logic: a countermeasure to reduce side channel leakage
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Masked dual-rail pre-charge logic: DPA-resistance without routing constraints
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Improved higher-order side-channel attacks with FPGA experiments
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Noise Reduction in Side Channel Attack Using Fourth-Order Cumulant
IEEE Transactions on Information Forensics and Security
A digital design flow for secure integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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FPGA design of side-channel analysis countermeasures using unmasked dual-rail with precharge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful differential placement and routing whereas both FPGA layout and FPGA EDA tools are not developed for such purposes. However, assessing the security level which can be achieved with them is an important issue, as it is directly related to the suitability to use commercial FPGA instead of proprietary custom FPGA for this kind of protection. In this article, we experimentally gave evidence that differential placement and routing of an FPGA implementation can be done with a granularity fine enough to improve the security gain. However, so far, this gain turned out to be lower for FPGAs than for ASICs. The solutions demonstrated in this article exploit the dual-output of modern FPGAs to achieve a better balance of dual-rail interconnections. However, we expect that an in-depth analysis of routing resources power consumption could still help reduce the interconnect differential leakage.