Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Examining Smart-Card Security under the Threat of Power Analysis Attacks
IEEE Transactions on Computers
Towards Sound Approaches to Counteract Power-Analysis Attacks
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
DES and Differential Power Analysis (The "Duplication" Method)
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Using Second-Order Power Analysis to Attack DPA Resistant Software
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
An Implementation of DES and AES, Secure against Some Attacks
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Power-Analysis Attack on an ASIC AES implementation
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
On the Masking Countermeasure and Higher-Order Power Analysis Attacks
ITCC '05 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'05) - Volume I - Volume 01
A side-channel analysis resistant description of the AES s-box
FSE'05 Proceedings of the 12th international conference on Fast Software Encryption
Side-channel leakage of masked CMOS gates
CT-RSA'05 Proceedings of the 2005 international conference on Topics in Cryptology
Gaussian Mixture Models for Higher-Order Side Channel Analysis
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Side Channel Cryptanalysis of a Higher Order Masking Scheme
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Block Ciphers Implementations Provably Secure Against Second Order Side Channel Analysis
Fast Software Encryption
Isolated WDDL: A Hiding Countermeasure for Differential Power Analysis on FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Dual-rail transition logic: A logic style for counteracting power analysis attacks
Computers and Electrical Engineering
Vulnerability modeling of cryptographic hardware to power analysis attacks
Integration, the VLSI Journal
Changing the odds against masked logic
SAC'06 Proceedings of the 13th international conference on Selected areas in cryptography
Power analysis attacks on MDPL and DRSL implementations
ICISC'07 Proceedings of the 10th international conference on Information security and cryptology
Power variance analysis breaks a masked ASIC implementation of AES
Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting dual-output programmable blocks to balance secure dual-rail logics
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
Leakage squeezing countermeasure against high-order attacks
WISTP'11 Proceedings of the 5th IFIP WG 11.2 international conference on Information security theory and practice: security and privacy of mobile devices in wireless communication
Thwarting higher-order side channel analysis with additive and multiplicative maskings
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Towards security limits in side-channel attacks
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Practical second-order DPA attacks for masked smart card implementations of block ciphers
CT-RSA'06 Proceedings of the 2006 The Cryptographers' Track at the RSA conference on Topics in Cryptology
Template attacks on masking—resistance is futile
CT-RSA'07 Proceedings of the 7th Cryptographers' track at the RSA conference on Topics in Cryptology
A first-order leak-free masking countermeasure
CT-RSA'12 Proceedings of the 12th conference on Topics in Cryptology
Blind cartography for side channel attacks: cross-correlation cartography
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Optimal first-order masking with linear and non-linear bijections
AFRICACRYPT'12 Proceedings of the 5th international conference on Cryptology in Africa
Analyzing side channel leakage of masked implementations with stochastic methods
ESORICS'07 Proceedings of the 12th European conference on Research in Computer Security
On the use of shamir's secret sharing against side-channel analysis
CARDIS'12 Proceedings of the 11th international conference on Smart Card Research and Advanced Applications
RSM: a small and fast countermeasure for AES, secure against 1st and 2nd-order zero-offset SCAs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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We demonstrate that masking a block cipher implementation does not sufficiently improve its security against side-channel attacks. Under exactly the same hypotheses as in a Differential Power Analysis (DPA), we describe an improvement of the previously introduced higher-order techniques allowing us to defeat masked implementations in a low (i.e. practically tractable) number of measurements. The proposed technique is based on the efficient use of the statistical distributions of the power consumption in an actual design. It is confirmed both by theoretical predictions and practical experiments against FPGA devices.