Towards Sound Approaches to Counteract Power-Analysis Attacks
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
DES and Differential Power Analysis (The "Duplication" Method)
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Using Second-Order Power Analysis to Attack DPA Resistant Software
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
Electromagnetic Analysis: Concrete Results
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Tamper resistance: a cautionary note
WOEC'96 Proceedings of the 2nd conference on Proceedings of the Second USENIX Workshop on Electronic Commerce - Volume 2
Secure FPGA circuits using controlled placement and routing
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Divided Backend Duplication Methodology for Balanced Dual Rail Routing
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA
IOLTS '08 Proceedings of the 2008 14th IEEE International On-Line Testing Symposium
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Statistical Analysis of Second Order Differential Power Analysis
IEEE Transactions on Computers
Using Optical Emission Analysis for Estimating Contribution to Power Analysis
FDTC '09 Proceedings of the 2009 Workshop on Fault Diagnosis and Tolerance in Cryptography
DPA Resistant AES on FPGA Using Partial DDL
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Enhancing correlation electromagnetic attack using planar near-field cartography
Proceedings of the Conference on Design, Automation and Test in Europe
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints
Proceedings of the Conference on Design, Automation and Test in Europe
When failure analysis meets side-channel attacks
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations
RECONFIG '11 Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs
Improved higher-order side-channel attacks with FPGA experiments
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Revisiting higher-order DPA attacks: multivariate mutual information analysis
CT-RSA'10 Proceedings of the 2010 international conference on Topics in Cryptology
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Side channel and fault injection attacks are major threats to cryptographic applications of embedded systems. Best performances for these attacks are achieved by focusing sensors or injectors on the sensible parts of the application, by means of dedicated methods to localise them. Few methods have been proposed in the past, and all of them aim at pinpointing the cryptoprocessor. However it could be interesting to exploit the activity of other parts of the application, in order to increase the attack's efficiency or to bypass its countermeasures. In this paper, we present a localisation method based on cross-correlation, which issues a list of areas of interest within the attacked device. It realizes an exhaustive analysis, since it may localise any module of the device, and not only those which perform cryptographic operations. Moreover, it also does not require a preliminary knowledge about the implementation, whereas some previous cartography methods require that the attacker could choose the cryptoprocessor inputs, which is not always possible. The method is experimentally validated using observations of the electromagnetic near field distribution over a Xilinx Virtex 5 FPGA. The matching between areas of interest and the application layout in the FPGA floorplan is confirmed by correlation analysis.