CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
Power Analysis, What Is Now Possible...
ASIACRYPT '00 Proceedings of the 6th International Conference on the Theory and Application of Cryptology and Information Security: Advances in Cryptology
On Boolean and Arithmetic Masking against Differential Power Analysis
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
Differential Power Analysis in the Presence of Hardware Countermeasures
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Evaluation on FPGA of triple rail logic robustness against DPA and DEMA
Proceedings of the Conference on Design, Automation and Test in Europe
DPA leakage models for CMOS logic circuits
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
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Side Channel Attacks (SCA) are a serious threat against security of cryptographic algorithms. Most of the countermeasures proposed to protect cryptosystems against these attacks, are efficient but present a significant area and power consumption overhead. The registers being the main weakness of cryptosystems, the source of leaks the more easily exploitable, we proposed a secure DFF which reduces leaks. In this paper, we present this countermeasure which considerably increases the robustness of cryptographic algorithms against side channel attacks. Moreover, the area and power overhead of our secure DFF in a cryptosystem is attractive.