Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
High-density reachability analysis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
A Discipline of Programming
Combining Software and Hardware Verification Techniques
Formal Methods in System Design
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Efficient Computation of Recurrence Diameters
VMCAI 2003 Proceedings of the 4th International Conference on Verification, Model Checking, and Abstract Interpretation
Partial-Order Reduction in Symbolic State Space Exploration
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Combining Symmetry Reduction and Under-Approximation for Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
SAT Based Abstraction-Refinement Using ILP and Machine Learning Techniques
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Stochastic Colored Petri Net Models for Rainbow Optical Networks
Application of Petri Nets to Communication Networks, Advances in Petri Nets
A Stubborn Attack On State Explosion
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
An Iterative Approach to Language Containment
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Combining Partial Order Reductions with On-the-fly Model-Checking
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Using Partial Orders for the Efficient Verification of Deadlock Freedom and Safety Properties
CAV '91 Proceedings of the 3rd International Workshop on Computer Aided Verification
A Mechanized Proof Environment for the Convenient Computations Proof Method
Formal Methods in System Design
Counterexample-guided abstraction refinement for symbolic model checking
Journal of the ACM (JACM)
Verification of distributed programs using representative interleaving sequences
Distributed Computing
Automatic abstraction without counterexamples
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
A calculus of logical relations for over- and underapproximating static analyses
Science of Computer Programming
Efficient Modeling of Concurrent Systems in BMC
SPIN '08 Proceedings of the 15th international workshop on Model Checking Software
An approach for extracting a small unsatisfiable core
Formal Methods in System Design
Linear-Time Reductions of Resolution Proofs
HVC '08 Proceedings of the 4th International Haifa Verification Conference on Hardware and Software: Verification and Testing
Monotonic Partial Order Reduction: An Optimal Symbolic Partial Order Reduction Technique
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Reduction of Verification Conditions for Concurrent System Using Mutually Atomic Transactions
Proceedings of the 16th International SPIN Workshop on Model Checking Software
Symbolic pruning of concurrent program executions
Proceedings of the the 7th joint meeting of the European software engineering conference and the ACM SIGSOFT symposium on The foundations of software engineering
Underapproximation for model-checking based on universal circuits
Information and Computation
Underapproximation for model-checking based on random cryptographic constructions
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Bug hunting with false negatives
IFM'07 Proceedings of the 6th international conference on Integrated formal methods
Peephole partial order reduction
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Slicing and dicing bugs in concurrent programs
Proceedings of the 32nd ACM/IEEE International Conference on Software Engineering - Volume 2
SMT-based bounded model checking for multi-threaded software in embedded systems
Proceedings of the 32nd ACM/IEEE International Conference on Software Engineering - Volume 2
Compositional reachability analysis for efficient modular verification of asynchronous designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 38th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Trace-driven verification of multithreaded programs
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
Verifying multi-threaded software using smt-based context-bounded model checking
Proceedings of the 33rd International Conference on Software Engineering
Computing small unsatisfiable cores in satisfiability modulo theories
Journal of Artificial Intelligence Research
Checking bounded reachability in asynchronous systems by symbolic event tracing
VMCAI'10 Proceedings of the 11th international conference on Verification, Model Checking, and Abstract Interpretation
On sampled semantics of timed systems
FSTTCS '05 Proceedings of the 25th international conference on Foundations of Software Technology and Theoretical Computer Science
Deriving small unsatisfiable cores with dominators
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Symbolic model checking of concurrent programs using partial orders and on-the-fly transactions
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Concrete model checking with abstract matching and refinement
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Symbolic model checking for asynchronous boolean programs
SPIN'05 Proceedings of the 12th international conference on Model Checking Software
Under-approximations of computations in real numbers based on generalized affine arithmetic
SAS'07 Proceedings of the 14th international conference on Static Analysis
SAS'07 Proceedings of the 14th international conference on Static Analysis
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This paper presents a procedure for the verification of multi-process systems based on considering a series of underapproximated models. The procedure checks models with an increasing set of allowed interleavings of the given set of processes, starting from a single interleaving. The procedure relies on SAT solvers' ability to produce proofs of unsatisfiability: from these proofs it derives information that guides the process of adding interleavings on the one hand, and determines termination on the other. The presented approach is integrated in a SAT-based Bounded Model Checking (BMC) framework. Thus, a BMC formulation of a multi-process system is introduced, which allows controlling which interleavings are considered. Preliminary experimental results demonstrate the practical impact of the presented method.