Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Object lifecycles: modeling the world in states
Object lifecycles: modeling the world in states
A fast and effective heuristic for the feedback arc set problem
Information Processing Letters
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Stutter-invariant temporal properties are expressible without the next-time operator
Information Processing Letters
Approximation alogorithms for the maximum acyclic subgraph problem
SODA '90 Proceedings of the first annual ACM-SIAM symposium on Discrete algorithms
IEEE Standard Description Language Based on the VERILOG Hardware Description Language, 1364-1995
IEEE Standard Description Language Based on the VERILOG Hardware Description Language, 1364-1995
Symbolic Model Checking
On the temporal analysis of fairness
POPL '80 Proceedings of the 7th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
A Formal Object-Oriented Analysis for Software Reliability: Design for Verification
FASE '01 Proceedings of the 4th International Conference on Fundamental Approaches to Software Engineering
An improvement in formal verification
Proceedings of the 7th IFIP WG6.1 International Conference on Formal Description Techniques VII
Static Partial Order Reduction
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Formal Verification of a Partial-Order Reduction Technique for Model Checking
TACAs '96 Proceedings of the Second International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Partial-Order Reduction in Symbolic State Space Exploration
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
A Stubborn Attack On State Explosion
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Refining Dependencies Improves Partial-Order Verification Methods (Extended Abstract)
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Modelling Asynchrony with a Synchronous Model
Proceedings of the 7th International Conference on Computer Aided Verification
Compressing Transitions for Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Proof-guided underapproximation-widening for multi-process systems
Proceedings of the 32nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
PLTL-partitioned model checking for reactive systems under fairness assumptions
ACM Transactions on Embedded Computing Systems (TECS)
Automatic formal model generation and analysis of SDL
SDL'03 Proceedings of the 11th international conference on System design
An automata-theoretic approach to hardware/software co-verification
FASE'10 Proceedings of the 13th international conference on Fundamental Approaches to Software Engineering
Efficient reachability analysis of büchi pushdown systems for hardware/software co-verification
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
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Combining verification methods developed separately for software and hardware is motivated by the industry's need for a technology that would make formal verification of realistic software/hardware co-designs practical. We focus on techniques that have proved successful in each of the two domains: BDD-based symbolic model checking for hardware verification and partial order reduction for the verification of concurrent software programs. In this paper, we first suggest a modification of partial order reduction, allowing its combination with any BDD-based verification tool, and then describe a co-verification methodology developed using these techniques jointly. Our experimental results demonstrate the efficiency of this combined verification technique, and suggest that for moderate–size systems the method is ready for industrial application.