Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Proceedings of the Fourth Annual Symposium on Logic in computer science
Design and validation of computer protocols
Design and validation of computer protocols
The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Model checking and modular verification
ACM Transactions on Programming Languages and Systems (TOPLAS)
Model checking and abstraction
ACM Transactions on Programming Languages and Systems (TOPLAS)
Temporal verification of reactive systems: safety
Temporal verification of reactive systems: safety
Verification of liveness properties using compositional reachability analysis
ESEC '97/FSE-5 Proceedings of the 6th European SOFTWARE ENGINEERING conference held jointly with the 5th ACM SIGSOFT international symposium on Foundations of software engineering
Checking that finite state concurrent programs satisfy their linear specification
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Model checking
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Symbolic Model Checking
Combining Software and Hardware Verification Techniques
Formal Methods in System Design
CONCUR '97 Proceedings of the 8th International Conference on Concurrency Theory
Partial-Order Methods for Temporal Verification
CONCUR '93 Proceedings of the 4th International Conference on Concurrency Theory
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
Synchronized Parallel Composition of Event Systems in B
ZB '02 Proceedings of the 2nd International Conference of B and Z Users on Formal Specification and Development in Z and B
Introducing Dynamic Constraints in B
B '98 Proceedings of the Second International B Conference on Recent Advances in the Development and Use of the B Method
Checking for Language Inclusion Using Simulation Preorders
CAV '91 Proceedings of the 3rd International Workshop on Computer Aided Verification
Verification of a Multiplier: 64 Bits and Beyond
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Proceedings of the 7th International Conference on Computer Aided Verification
Verification of Fair Transisiton Systems
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Algorithmic Verification of Linear Temporal Logic Specifications
ICALP '98 Proceedings of the 25th International Colloquium on Automata, Languages and Programming
An efficient verification method for parallel and distributed programs
Linear Time, Branching Time and Partial Order in Logics and Models for Concurrency, School/Workshop
Model Checking with Strong Fairness,
Model Checking with Strong Fairness,
Refinement preserves PLTL properties
ZB'03 Proceedings of the 3rd international conference on Formal specification and development in Z and B
Partitioned PLTL model-checking for refined transition systems
Information and Computation
Heuristics to verify LTL properties of hierarchical systems
VECoS'08 Proceedings of the Second international conference on Verification and Evaluation of Computer and Communication Systems
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We are interested in verifying dynamic properties of finite state reactive systems under fairness assumptions by model checking. The systems we want to verify are specified through a top-down refinement process.In order to deal with the state explosion problem, we have proposed in previous works to partition the reachability graph and to perform the verification on each part separately. Moreover, we have defined a class, called Bmod, of dynamic properties that are verifiable by parts, whatever the partition. We decide if a property P belongs to Bmod by looking at the form of the Büchi automaton that accepts ¬P. However, when a property P belongs to Bmod, the property f ⇒ P, where f is a fairness assumption, does not necessarily belong to Bmod.In this paper, we propose to use the refinement process in order to build the parts on which the verification has to be performed. We then show that with such a partition, if a property P is verifiable by parts and if f is the expression of the fairness assumptions on a system, then the property f ⇒ P is still verifiable by parts.This approach is illustrated by its application to the chip card protocol T = 1 using the B engineering design language.