Partitioned PLTL model-checking for refined transition systems

  • Authors:

  • J. Julliand;P. -A. Masson;E. Oudot

  • Affiliations:

  • LIFC -- Laboratoire d'Informatique de l'Université de Franche-Comté 16, route de Gray, 25 030 Besancon Cedex, France;LIFC -- Laboratoire d'Informatique de l'Université de Franche-Comté 16, route de Gray, 25 030 Besancon Cedex, France;LIFC -- Laboratoire d'Informatique de l'Université de Franche-Comté 16, route de Gray, 25 030 Besancon Cedex, France

  • Venue:
  • Information and Computation
  • Year:
  • 2009

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Abstract

This paper is about the verification of dynamic properties by model-checking for finite state reactive systems. Properties are expressed as PLTL formulae. Systems are specified through a top-down refinement process. In order to cope with the state explosion problem, we propose partitioning the state space to be verified and to verify the properties independently on each part. Properties that are such that if they hold on every part then they hold for the whole system are called verifiable by parts. In a previous paper, we presented a class of interesting PLTL properties that are always verifiable by parts. That is, they are verifiable by parts with any partitioning of the state space. In addition to these properties, some properties are verifiable by parts on a system provided with a particular partitioning. In this paper, we propose a partitioning of the state space of a system that is guided by the refinement process. We introduce an extended class of PLTL properties that are verifiable by parts with regard to this partitioning. This class includes the first one. In particular, the new class includes liveness properties under fairness assumptions. This class is defined from Buchi automata that accept the language of the negations of the properties. Our work is illustrated by its application to a chip card protocol called T=1. This protocol is specified through successive refinements.