NuSMV 2: An OpenSource Tool for Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Logic in Computer Science: Modelling and Reasoning about Systems
Logic in Computer Science: Modelling and Reasoning about Systems
Verification of timed circuits with failure-directed abstractions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Reliability is one of the major concerns in the design of embedded systems. Formal verification by model checking is of a great advantage in verifying the correctness of computer system, whether they are hardware, software or a combination. The paper reports the design and development of an intelligent telephone alarm that is a single-chip computer system, and the formal verification of communication protocol is described based on the model checker NuSMV.