Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Model checking and modular verification
ACM Transactions on Programming Languages and Systems (TOPLAS)
Modeling design constraints and biasing in simulation using BDDs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Formal property verification by abstraction refinement with formal, simulation and hybrid engines
Proceedings of the 38th annual Design Automation Conference
Deriving a simulation input generator and a coverage metric from a formal specification
Proceedings of the 39th annual Design Automation Conference
Monitor-Based Formal Specification of PCI
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
A Compositional Rule for Hardware Design Refinement
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
MOCHA: Modularity in Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Building Circuits from Relations
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Word problems requiring exponential time(Preliminary Report)
STOC '73 Proceedings of the fifth annual ACM symposium on Theory of computing
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Supporting sequential assumptions in hybrid verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal constraint-preserving netlist simplification
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Learning from Constraints for Formal Property Checking
Journal of Electronic Testing: Theory and Applications
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To prove system correctness, assumptions made in verifying a blockmust be cleared by verifying that the block's environment guaranteesthem. Conversely, guarantees enforced by a block may be usedas assumptions for its environment. Block level interface specificationsthus serve as both assumptions and guarantees in compositionalverification. Traditionally, such specifications have beenrepresented as monitors or checkers. In this paper, we propose analternative representation using generators. Novel algorithms arepresented for simulation and formal verification. We argue that forsimulation, representation as a generator can be more efficient thanas a checker - both asymptotically and practically. We also identifya subset of generators that can be efficiently handled using formaltechniques. Experimental results are given for some benchmarkexamples and industrial case studies.