win and sin: predicate transformers for concurrency
ACM Transactions on Programming Languages and Systems (TOPLAS)
The existence of refinement mappings
Theoretical Computer Science
Verifying the summit bus converter protocols with symbolic model checking
Formal Methods in System Design
The formal verification of a pipelined double-precision IEEE floating-point multiplier
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Formal Methods in System Design
Deciding Combinations of Theories
Journal of the ACM (JACM)
Simplification by Cooperating Decision Procedures
ACM Transactions on Programming Languages and Systems (TOPLAS)
A Formal Approach to Hardware Design
A Formal Approach to Hardware Design
Digital Computer Arithmetic
A Discipline of Programming
Experience with Embedding Hardware Description Languages in HOL
Proceedings of the IFIP TC10/WG 10.2 International Conference on Theorem Provers in Circuit Design: Theory, Practice and Experience
Verifying Distributed Directory-Based Cahce Coherence Protocols: S3.mp, a Case Study
Euro-Par '95 Proceedings of the First International Euro-Par Conference on Parallel Processing
An Integration of Model Checking with Automated Proof Checking
Proceedings of the 7th International Conference on Computer Aided Verification
STeP: Deductive-Algorithmic Verification of Reactive and Real-Time Systems
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
A Platform for Combining Deductive with Algorithmic Verification
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
An Old-Fashioned Recipe for Real Time
Proceedings of the Real-Time: Theory in Practice, REX Workshop
PVS: A Prototype Verification System
CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
Verifying a Self-Timed Divider
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
A simple theorem prover based on symbolic trajectory evaluation and BDD's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present a deductive verification framework that combines deductive reasoning, general purpose decision procedures, and domain-specific reasoning. We address the integration of formal as well as informal domain-specific reasoning, which is encapsulated in the form of user-defined inference rules. To demonstrate our approach, we describe the verification of a SRT divider where a transistor-level implementation with timing is shown to be a refinement of its high-level specification.