Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
A Formal Approach to Hardware Design
A Formal Approach to Hardware Design
The Definition of Standard ML
The Counterflow Pipeline Processor Architecture
IEEE Design & Test
Mechanized Verification of Circuit Descriptions Using the Larch Prover
Proceedings of the IFIP TC10/WG 10.2 International Conference on Theorem Provers in Circuit Design: Theory, Practice and Experience
Using Synchronized Transitions for Simulation and Timing Verification
Proceedings of the Second IFIP WG10.2/WG10.5 Workshop on Designing Correct Circuits
Higher-Level Specification and Verification with BDDs
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
Automatic Verification of Asynchronous Circuits
Automatic Verification of Asynchronous Circuits
VOSS - A Formal Hardware Verification System User''s Guide
VOSS - A Formal Hardware Verification System User''s Guide
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The verification of asynchronous designs is difficult, since design errors may only be manifested under rare circumstances. We show how asynchronous designs can be modeled as programs in the general-purpose hardware description language Synchronized Transitions, translated into the verification language, and how this representation facilitates rigorous and efficient verification of the designs.