A Spanning Tree Carry Lookahead Adder
IEEE Transactions on Computers - Special issue on computer arithmetic
Performance of Synchronous and Asynchronous Schemes for VLSI Systems
IEEE Transactions on Computers
Asynchronous Circuits for Low Power: A DCC Error Corrector
IEEE Design & Test
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
A formal approach to designing delay-insensitive circuits
Distributed Computing
Computer arithmetic and hardware: "off the shelf" microprocessors versus "custom hardware"
Theoretical Computer Science
VLSI Implementation of a Low-Power High-Speed Self-Timed Adder
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
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Addition techniques are divided into fixed-time and variable-time ones. While variable time techniques can achieve log2(N) average addition time for N-bit operands, the hardware overhead have always made fixed-time adders preferable, such as Carry Lookahead and Carry Select.We present a new variable-time addition technique whose average delay is much lower than log2(N) and whose overhead is lower than the one of a CLA adder. The new approach is made feasible by a proper application of VLSI dynamic logic design. We show the mathematical proof, the logic implementation, and the VLSI realization of the new adder. We report circuit simulation results and their comparison with the analytical model.