An evaluation of asynchronous addition
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Design of synchronous and asynchronous variable-latency pipelined multipliers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical Carry Lookahead Adders
IEEE Transactions on Computers
Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Proceedings of the 43rd annual Design Automation Conference
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Some New Results on Average Worst Case Carry
IEEE Transactions on Computers
Variable-latency adder (VL-adder) designs for low power and NBTI tolerance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Synchronous early-completion-prediction adders (ECPAs) are used for high clock rate and high-precision DSP datapaths, as they allow a dominant amount of single-cycle operations even if the worst-case carry propagation delay is longer than the clock period. Previous works have also demonstrated ECPA advantages for average leakage reduction and NBTI effects reduction in nanoscale CMOS technologies. This paper illustrates a general systematic methodology to design ECPA units, targeting nanoscale CMOS technologies, which is not available in the current literature yet. The method is fully compatible with standard VLSI macrocell design tools and standard adder structures and includes automatic definition of critical test patterns for postlayout verification. A design example is included, reporting speed and power data superior to previous works.